IEEE Electronics Packaging Society

Advanced X-ray Imaging Technologies for Heterogeneous 3D IC Package Metrology and Inspection

Advanced X-ray Imaging Technologies for Heterogeneous 3D IC Package Metrology and Inspection 1137 642 ieeeeduweek

The advent of 3D Heterogeneous Integration (3DHI) in advanced packaging and wafer-level IC packaging introduces significant challenges for inline defect inspection and offline failure analysis. The 3D stacking and wafer bonding processes create optically opaque structures, necessitating techniques like x-rays to penetrate multiple buried layers for defect detection.

IEEE-Affiliated Group Name: EPS

URL: https://resourcecenter.eps.ieee.org/education/webinars/epsvid1170

Process Development and Reliability Investigations for Scaling 3D Interconnects in Advanced Semiconductor Packaging

Process Development and Reliability Investigations for Scaling 3D Interconnects in Advanced Semiconductor Packaging 1144 631 ieeeeduweek

Advanced semiconductor packaging is playing a crucial role to drive system performance and functionality. With the increasing demand for emerging and growing computing needs, heterogeneous three-dimensional (3D) integration with fine-pitch, high-density interconnections, and multi-chip stacks are very promising in the future. The aggressive interconnects pitch scaling and nanoscale via interconnections make the process development and reliability more and more challenging.

IEEE-Affiliated Group Name: EPS

URL: https://resourcecenter.eps.ieee.org/education/webinars/epsvid1160

Recent Advances and Trends in Advanced Packaging

Recent Advances and Trends in Advanced Packaging 1131 631 ieeeeduweek

In this lecture, semiconductor advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance and are grouped into 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration. Key enabling technologies such as flip chip and fan-out are briefly mentioned. The trends and challenges (opportunities) of advanced packaging are discussed. Also, in this lecture, chiplet design and heterogeneous integration packaging are defined.

IEEE-Affiliated Group Name: EPS

URL: https://resourcecenter.eps.ieee.org/education/webinars/epsvid0480

Photonics Systems for High Performance – CPO, Towards Photonics Chiplets (Video)

Photonics Systems for High Performance – CPO, Towards Photonics Chiplets (Video) 1138 637 ieeeeduweek

A major hurdle in developing next-generation systems for high-performance applications and industries that require handling large, secure data – such as System-in-Package (SiP) and System-on-Chip (SoC) – is the absence of low-latency, high-bandwidth, and high-density off-chip/chiplet/core interconnects.

IEEE-Affiliated Group Name: EPS

URL: https://resourcecenter.eps.ieee.org/education/webinars/eps_ed_web_pshp_102424

EPS PhD Fellowship

EPS PhD Fellowship 252 81 ieeeeduweek

Support PhD level study and research within the Electronics Packaging Society’s field of interest.

IEEE-Affiliated Group Name: IEEE Electronics Packaging Society

URL: https://eps.ieee.org/awards/phd-fellowship.html

EPS Certificate Program

EPS Certificate Program 252 81 ieeeeduweek

certificate program for early, mid and late career

IEEE-Affiliated Group Name: IEEE Electronics Packaging Society

URL: https://eps.ieee.org/education/eps-certificate-program.html

Webinars on Resource Center

Webinars on Resource Center 252 81 ieeeeduweek

webinars in electronics packaging

IEEE-Affiliated Group Name: IEEE Electronics Packaging Society

URL: https://resourcecenter.eps.ieee.org/education/webinars.html