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VHDL Circuit Design, Simulation and FPGA Programming Using VIVADO Course
February 15 @ 11:00 am – 12:00 pm
Course Format: Live Webinar, 10 sessions, 1 hour per session
Times and Dates: 11AM (ET) February 15, 17, 22, 24, March 1, 3, 8, 10, 15, 17
Introduction: In this course VHDL circuit design language will be taught. VIVADO Platform will be used for VHDL coding, simulation and FPGA programming. The attendee should have basic knowledge of digital circuit design. VHDL language is an hardware design language. Its popularity is increasing in years. It is used to program FPGA devices. It is not exaggerating to say that most of the future electronic systems will include FPGA devices in their structures since FPGA devices are flexible, reconfigurable platforms for hardware designs. The attendee taking this course will learn VHDL language and he or she will be able to make digital circuit design using VHDL language. Besides, the attendee will learn how to program FPGA devices for circuits designed using VHDL.
Prerequisite: The one who is interested in taking this course should have basic knowledge of digital logic design. He or She should be familiar with the terms binary encoders, decoders, multiplexers, counters, registers, etc.
- Entity, Architecture and VHDL Operators
- Project Creation Using VIVADO, Schematic, Synthesis
- Internal Structure of FPGAs, LUTs, Slices
- Combinational Logic Circuit Design and Concurrent Coding in VHDL
- Testbench Writing and Simulation of VHDL Codes Using VIVADO
- Constraint Files and FPGA Programming with VIVADO
- User Defined Data Types in VHDL
- Sequential Circuit Implementation in VHDL
- Frequency Division in VHDL
- Testing Sequential Logic Circuits on VIVADO
- Packages, Components, Functions, and Procedures in VHDL
- Fixed and Floating Point numbers in VHDL
Target Audience: Electronic and Communication Engineers, electronic engineers, computer engineers, engineers working in communication industry