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“Polynomial Formal Verification: Ensuring Correctness under Resource Constraints” by Rolf Drechsler

April 19 @ 9:00 am10:00 am

We review recent developments in formal verification techniques and give a comprehensive overview of Polynomial Formal Verification (PFV). In PFV, polynomial upper bounds for the run-time and memory needed during the entire verification task hold. Thus, correctness under resource constraints can be ensured. We discuss the importance and advantages of PFV in the design flow. Formal methods on the bit-level and the word-level, and their complexities when used to verify different types of circuits.

Details

Date:
April 19
Time:
9:00 am – 10:00 am
Event Category:
Website:
https://ieee-ceda.org/event/polynomial-formal-verification-ensuring-correctness-under-resource-constraints-rolf-drechsler
Affiliated Group Name: CEDA
Type: Virtual Event

Other

Type
Virtual Event
Affiliated Group Name
CEDA
Level
Continuing and Professional Education